1. Field of the Invention
The present invention relates generally to an electrostatic protection device for a semiconductor circuit, and more particularly to a connection structure of an electrostatic protection device for preventing damage due to discharge of electrostatic charges.
2. Description of the Prior Art
A semiconductor integrated circuit (IC) could be damaged when it comes in contact with a charged human body or machine. An unhealthy dose of static electricity or electrostatic discharge (ESD) charges from a human body or a machine could be discharged into the semiconductor IC through its contacting external pin(s) and pad(s), such that an excessive current of large energy introduced into the semiconductor IC may cause the internal damage.
Therefore, an ESD protection device is typically formed in a semiconductor IC between a pad and its internal circuit in order to protect the important circuits from such electrostatic damage. An ESD protection device having a large area is preferred, since it will allow a larger-capacity current to pass to the ground preventing major damage to the internal circuitry. FIG. 1 shows an example of such an ESD protection device having a large area, which has a multi-finger structure of multiple transistors having common drains.
FIG. 1 shows the design of a conventional ESD protection device connected to a pad 1 of an IC. The ESD protection device as shown in FIG. 1 has the multi-finger structure and includes a plurality of NMOS “finger” transistors, where each “finger” transistor has a gate 2 such that a source 3 a common drain 4 are alternately arranged adjacent each gate 2 of each “finger” transistor. (Note that not every gate, source, and drain are labeled with 2, 3, 4 in FIG. 1, but they should be readily apparent from FIG. 1.) When ESD charges are generated, the ESD charges would flow in the direction labeled with arrows 10 through the metal wires M1˜M7 connected to the pad 1 and through the common drains 4 of the transistors in order to be discharged through the sources 3 into the well pickup 5, thereby preventing damage to the internal circuits of the semiconductor IC.
However, in the above-mentioned conventional structure for an ESD protection device, the pad 1 is connected to only one end of the common drain 4. Therefore, when excessive current flowing due to ESD charges is concentrated at the end of each common drain 4 connected to the pad 1, the metal wires M1˜M7 at the connected end may melt or the connected end of each drain 4 itself may be damaged by the ESD.
Further, the conventional structure as shown in FIG. 1 could be problematic when the excessive current passes through the pickup 5 surrounding the multi-fingered transistor structure. More specifically, the common drain connected to the fourth metal wire M4 located at the center of multi-fingered ESD protection device as shown in FIG. 1 is located the farthest away from the well pickup 5 in the X-axis direction; thus, a larger well resistance is present between the common drain connected to M4 and the well pickup 5 than between any of the other common drains and the well pickup 5. As a result, the entire NMOS “finger” transistors of the conventional ESD protection device may yield non-uniform results at the time of bipolar turn-on.